In various computer and memory related devices, it is common for elements to be connected by one or more busses for the transfer of data and commands. For example, in a flash memory device, such as a memory card or USB memory drive, the device itself will communicate through an interface acting a bus and within the device itself its component elements will communicate with busses. Taking the flash memory system example, this will often have a controller and one or more memory chips connected by one or more busses. In many such devices, a bus (usually a data bus) will be operable in differing widths. Thus, in the case of flash memories, although historically these started out having an interface that could transmit 8 bits at a time (or “×8”), some manufactures have increased the bus width to 16 lines (“×16”) for a higher data throughput. However, as some users will still only use a ×8 mode to reduce the number of lines routed between a memory and controller and save on the required board area, it can be useful to have system elements that function in both a ×8 and a ×16 mode.
In memory systems where power consumption is a concern, the technique of bus inversion is often employed. The power consumption depends upon the amount of transition for the bus lines: the greater the number of transitions, the more the power consumption. For example high to high, will consume less power than a transition from low to high or high to low. The idea of data inversion is to minimize the number of transitions in the bus, and the consequent power usage, by determining at each cycle whether to invert the data bus, along with an indication of this to the receiving end so that it knows to whether or not to re-invert data to be able to extract the correct content. This requires the system to determine for each transfer cycle whether or not to change the inversion of the bus, which can be accomplished by the process of “majority voting”. Various techniques related to data bus inversion and majority voting can be found in references such as U.S. Pat. No. 7,236,005 and US patent applications numbers 20040068594 and 20050188282. However, the various prior art techniques make no allowance for consideration of multiple bus widths in the majority voting and bus inversion process.